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WM5620L, WM5620
Production Data Sept. 1996 Rev 2
3 & 5V Quad 8-Bit Voltage Output DAC with Serial Interface
Description
WM5620L and WM5620 are quad 8-bit digital to analogue converters (DAC) controlled via a serial interface. Each DAC's output voltage range isprogrammable for either x1 or x 2 its reference input voltage, allowing near rail to rail operation for the x 2 output range. Separate high impedance buffered voltage reference inputs are provided for each DAC. WM5620L operates on a single supply voltage of 3 V while WM5620 operates on 5 V. WM5620/L interfaces to all popular microcontrollers and microprocessors via a three wire serial interface with CMOS compatible, schmitt trigger, digital inputs. An 11 bit command word comprises 2 DAC select bits, an output range selection bit and 8-bits of data. Individual or all DAC outputs are changed using WM5620/ L's double buffered DAC registers and the separate LOAD and LDAC inputs. DAC outputs are updated simultaneously by writing a complete set of new values and then pulsing the LDAC input. The DAC outputs are optimised for single supply operation and driving ground referenced loads. An internal power-on-reset function sets the DAC's input codes to zero at power up. Ideal in space critical applications WM5620/L is available in small outline and DIP packages for commercial (0oC to 70oC) and industrial (-40oC to 85oC) temperature ranges.
Features
* * * * * * * Four 8-bit voltage output DAC's Three wire serial interface Programmable x1 or x 2 output range. Power-on-reset sets outputs to zero Buffered voltage reference inputs Simultaneous DAC output update 14 pin SO or DIP package
Key Specifications
* Single supply operation: WM5620L : 3 V WM5620 : 5V 0 to 4 V output (x 2 output range) at 5 V VDD 0 to 2.5 V output (x 2 output range) at 3 V VDD Low power: 5.1 mW at 3 V, 10 mW at 5 V max. Guaranteed monotonic output
* * * *
Applications
* * * * * * Programmable d.c. voltage sources Digitally controlled attenuator/amplifier Signal synthesis Mobile communications Automatic test equipment Process control
Block Diagram
Ref A 2
14 VDD
DAC
9
12
x2
Latch
Latch
8
DACA
Ref B
3
DAC
9
Latch
Latch
8
x2
11
DACB
Ref C
4
DAC
9
10
x2
Latch
Latch
8
DACC
Ref D
5
DAC
9
Latch
Latch
8
x2
9
DACD
Clk Data Load
7 6 8 13 LDAC 1 GND Serial Interface Power-on-Reset
Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics standard terms and conditions
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
(c) 1996 Wolfson Microelectronics
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: admin@wolfson.co.uk www: http://www.wolfson.co.uk
WM5620L, WM5620
Pin Configuration
Top View N and D packages DEVICE WM5620CN WM5620CD WM5620IN WM5620ID WM5620LCN WM5620LCD WM5620LIN WM5620LID TEMP. RANGE 0oC to 70oC 0oC to 70oC -40o C to 85oC -40o C to 85oC 0oC to 70oC 0oC to 70oC -40o C to 85oC -40o C to 85oC PACKAGE 14 pin plastic DIP 14 pin plastic SO 14 pin plastic DIP 14 pin plastic SO 14 pin plastic DIP 14 pin plastic SO 14 pin plastic DIP 14 pin plastic SO
Ordering Information
Absolute Maximum Ratings (note 1) Supply Voltage (VDD - VGND) . . . . . . . . . . . . +7V Digital Inputs . . . . . . . . . . GND - 0.3 V, VDD + 0.3 V Reference inputs . . . . . . . GND - 0.3 V, VDD + 0.3 V
Operating temperature range, TA . . . . . . TMIN to TMAX WM5620_C_ . . . . . . . . . . . . . . . . 0oC to +70o C WM5620_I_ . . . . . . . . . . . . . . . . -40oC to +85o C Storage Temperature_ . . . . . . . . . . -50o C to +150o C Lead Temperature 1.6mm (1/16 inch) from case (soldering, 10 sec) . . . . . . . . . . . . . . . + 260o C
Recommended Operating Conditions
SYMBOL Supply voltage WM5620 Supply Voltage WM5620L Reference input range x1 gain DAC output load resistance to GND High level digital input voltage Low level digital input voltage Clock frequency VDD VDD VREF [A/B/C/D] RL VIH VIL FCLK MIN 4.75 2.7 10 0.8 VDD 0.8 1 NOMINAL 3.3 MAX 5.25 5.25 VDD - 1.5 UNIT V V V k V V MHz
Electrical Characteristics: WM5620
VDD = 5 V, GND = 0 V, VREF = 2 V, RL = 10 k, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER Power Supply Supply current Static Accuracy Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Zero-code error Zero-code error temperature coefficient Zero-code error supply rejection SYMBOL IDD TEST CONDITIONS VDD = 5V 8 8 DNL INL ZCE VREF = 2 V, Range x 2. (note 3) VREF = 2 V, Range x 2. (note 4) VREF = 2 V, Range x 2. (note 5) Input code = 00 Hex (note 6) Input code = 00 Hex (note 7) 0.1 0 10 0.5 0.9 1.0 30 MIN TYP MAX 2 UNIT mA Bits Bits LSB LSB mV V/O C mV/V
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WM5620L, WM5620
Electrical Characteristics: WM5620
VDD = 5V 5%, GND = 0 V, VREF = 2 V, RL = 10 k, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER Full scale error Full scale error temperature coefficient Full scale error supply rejection Output sink current Output source current Reference input current SYMBOL TEST CONDITIONS FSE VREF = 2 V, Range x 2. (note 8) Input code = FF Hex (note 9) Input code= FF Hex, (note 10) Each DAC output MIN TYP 25 0.5 20 2 10 MAX 60 UNIT mV V/OC mV/V A mA A
IO(SINK) IO(SOURCE) IREF VDD=5V, VREF=2V
Electrical Characteristics: WM5620L
VDD = 3V, GND = 0 V, VREF =1.25 V, RL = 10 k, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER Power Supply Supply current Static Accuracy Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Zero-code error Zero-code error temperature coefficient Full scale error Full scale error temperature coefficient Output sink current Output source current Ref. input current SYMBOL IDD TEST CONDITIONS VDD = 3.3V 8 8 DNL INL ZCE VREF = 1.25 V, Range x 2. (note 3) VREF = 1.25 V, Range x 2. (note 4) VREF = 1.25 V, Range x 2. (note 5) Input code = 00 Hex (note 6) VREF = 1.25 V, Range x 2. (note 8) Input code = FF Hex (note 9) 20 1 10 0.9 1.0 30 10 60 25 MIN TYP MAX 2 UNIT mA Bits Bits LSB LSB mV V/OC mV V/OC A mA A
0
FSE
IO(SINK) Each DAC output IO(SOURCE) IREF VDD = 3.3V; Vref = 1.5V
Electrical Characteristics: WM5620 & WM5620L
VDD = 2.7V to 5.5V, GND = 0 V, RL = 10 k, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER Digital Inputs High level input current Low level input current Input capacitance Timing Parameters Data input setup time Data input hold time CLK to Load Load to CLK Load duration LDAC duration Load to LDAC SYMBOL IIH IIL CI tSD tHD tHL tSL tWL tWD tLD TEST CONDITIONS VI = VDD VI = 0V 15 50 50 50 50 250 250 0 MIN TYP MAX 10 10 UNIT A A pF ns ns ns ns ns ns ns
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WM5620L, WM5620
Electrical Characteristics: WM5620 & WM5620L
VDD = 2.7V to 5.5V, GND = 0 V, RL = 10 k, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS Reference Inputs A, B, C, D, inputs Reference input voltage VREF Reference input A, B, C, D, inputs capacitance Reference feedthrough A, B, C, D, inputs (note 11) Channel to channel A, B, C, D, inputs (note 12) isolation Dynamic Performance Output settling time To 1/2 LSB, VDD = 3 V & 5V (note13) Output slew rate Input bandwidth (note 14) Large Signal Bandwidth Measured at -3dB point Digital Crosstalk Clk = 1MHz sq wave measured at DACA - DACD MIN GND 15 - 60 -60 TYP MAX VDD - 1.5 UNIT V pF dB dB
10 1 100 100 -50
s V/s kHz kHz dB
Electrical Characteristics: WM5620 & WM5620L
Notes: 1. Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating range limits are given under Recommended Operating Conditions. Guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. 2. Total Unadjusted Error is the sum of integral linearity error, zero code error and full scale error over the input code range. 3. Differential Nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 4. Integral Nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors). 5. Zero code error is the deviation from zero voltage output when the digital input code is zero.
(continued)
6. Zero code error temperature coefficient is given by: ZCETC = (ZCE(Tmax) - ZCE(Tmin))/VREF x 106 / (Tmax - Tmin) 7. Zero-code Error Rejection Ratio (ZCE-RR) is measured by varying the VDD voltage, from 4.5 to 5.5 V d.c., and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Full-scale error is the deviation from the ideal fullscale output (VREF - 1 LSB) with an output load of 10k 9. Full-Scale Temperature Coefficient is given by: FSETC = (FSE(Tmax) - FSE(Tmin))/VREF x 106/(Tmax Tmin) 10. Full Scale Error Rejection Ratio (FSE-RR) is measured by varying the VDD voltage, from 4.5 to 5.5 V d.c., and measuring the proportion of this signal imposed on the full-scale output voltage.
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WM5620L, WM5620
Electrical Characteristics: WM5620 & WM5620L (continued)
11 Reference feedthrough is measured at a DAC output with an input code = 00 Hex with a VREF input = 1 Vdc + 1 VPP at 10kHz 12. Channel to channel isolation is measured at a DAC output with an input code of one DAC to FF Hex and the code oa all other DACs to oo Hex with a VREF input = 1 Vdc + 1 Vpp at 10kHz 13 Setting time is the time for the output signal to remain within 0.5 LSB of the final measurement value for a digital input code change of 00 Hex to FF Hex. For WM 5620: VDD = 5V, VREF = 2V and range = x 2. For WM5620L: VDD = 3, VREF = 1.25V and range = x 2. 14 Reference bandwidth is the -3dB bandwidth with an input at VREF = 1.25 Vdc =+ 2 Vpp with a digital input code of full-scale
Parameter Measurement Information
DACA DACB DACC DACD 10K CL - 100pF
Slewing Settling Time and Linearity Measurements
Typical Performance Characteristics
Typical DNL, INL and TUE * at VDD = 5 V D ifferential Nonlinearit y
0.2 Error (lsb) 0.1 0 -0.1 -0.2 0 32 64 96 128 160 192 224 256 Input Code
V DD = 5 V , V ref = 2.5 V , Range x 1, TA = 25OC
Inte gral No nline arit y
V DD = 5 V , V ref = 2.5 V , Range = x 1, T A = 25OC
0.2 Error (lsb) 0.1 0 -0.1 -0.2 0 32 64 96 128 160 192 224 256 Input Code
Tot al Unad just ed Error
V DD = 5 V , V ref = 2.5 V , Range = x 1, TA = 25O C
D iffe re nt ial Nonline arit y
V DD = 5 V , V ref = 2 V , Range = x 2, TA = 25OC
Error (lsb)
0.5 Error (lsb) 0.25 0 -0.25 -0.5 0 32 64 96 128 160 192 224 256 Input Code
0.2 0.1 0 -0.1 -0.2 0 32 64 96 128 160 192 224 256 Input Code
* see note 2
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WM5620L, WM5620
Typical Performance Characteristics (Continued)
Typical DNL, INL and TUE * at VDD = 5 V Inte gral Nonline arit y
V DD = 5 V , V ref = 2 V , Range = x 2, TA = 25 C
O
To tal Unadjuste d Error
V DD = 5 V , V ref = 2 V , Range = x 2, TA = 25OC
0.2 Error (lsb) Error (lsb) 0.1 0 -0.1 -0.2 0 32 64 96 128 160 192 224 256 Input Code
0.5 0.25 0 -0.25 -0.5 0 32 64 96 128 160 192 224 256 Input Code
Typical DNL, INL and TUE at VDD = 3 V D iffe re nt ial Nonline arit y
V DD = 3 V , V ref = 1.25 V , Range x 2, TA = 25OC
Inte gral Nonline arit y
V DD = 3 V , V ref = 1.25 V , Range x 2, TA = 25OC
0.2 Error (lsb) 0.1 0 -0.1 -0.2 0 32 64 96 128 160 192 224 256 Input Code Error (lsb)
0.2 0.1 0 -0.1 -0.2 0 32 64 96 128 160 192 224 256 Input Code
To tal Unadjuste d Error
V DD = 3 V , V ref = 1.25 V , Range x 2, TA = 25OC
0.5 Error (lsb) 0.25 0 -0.25 -0.5 0 32 64 96 128 160 192 224 256 Input Code
Out put Source Current v s Out put Voltage
8 7 6 1.2 1.15 1.1
Supply Current v s Temperat ure
Iout (mA)
IDD (mA)
5 4 3 2 1 0 0 1 2 3 4 5
V DD = 5 V TA = 25OC V ref= 2 V Range = x 2 Input code = 255
1.05 1 0.95 0.9 0.85 0.8 -50
Range = x 2 Input code = 255
V DD = 5 V V ref = 2 V
V DD = 3 V V ref = 1.25 V
0
50
100
Vout (V)
Tempera ture ( O C)
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WM5620L, WM5620
Typical Performance Characteristics (Continued)
Large Signal Fre que ncy Re sponse
0 -2 -4 10 0
Small Signal Frequency Response
Relative Gain (dB)
-6 -8 -10 -12 -14 -16 -18 -20 1 10 100 1000
V DD = 5 V TA = 25OC V ref = 1.25 Vdc + 2 V pp Input Code = 255
Relative Gain (dB)
-10 -20 -30 -40 -50 -60 1 10 100 1000 10000
V DD = 5 V TA = 25 OC V ref = 2 V dc + 0.5 V pp Input code = 255
Frequency (kHz)
Freq uency (kHz)
Positive Rise and Settling Time VDD = 3 V
Negative Fall and Settling Time VDD = 3 V
500 mV/Vert. div 2 s/Hor. div
VDD = 3 V TA = 25OC code 00 to FF Hex Range = x 2 Vref = 1.25 V
500 mV/Vert. div 5 s/Hor. div
VDD = 3 V TA = 25OC code FF to 00 Hex Range = x 2 Vref = 1.25 V
Rise time = 2.05 s, Positive slew rate = 0.96 s Settling time = 4.5 s Positive Rise and Settling Time VDD = 5 V
Fall time = 4.25 s, Negative slew rate = 0.46 s Settling time = 8.5 s Negative Fall and Settling Time VDD = 5 V
1 V/Vert. div 2 s/Hor. div VDD = 5 V TA = 25OC code 00 to FF Hex Range = x 2 Vref = 2 V
VDD = 5 V TA = 25OC code FF to 00 Hex Range = x 2 Vref = 2 V
1 V/Vert. div 5 s/Hor. div
Rise time = 2.4 s, Positive slew rate = 1.0 s Settling time = 5.8 s
Fall time = 5.0 s, Negative slew rate = 0.63 s Settling time = 9.5 s
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WM5620L, WM5620
Equivalent Input and Output Circuits
Timing Waveforms
Data Input Timing Load and LDAC Timing
CLK tSD
50 %
CLK
50 %
tHD
Load
tHL
tWL
tSL
Data
tLD
tWD
LDAC
Timing Diagrams
1 CLK 2 3 4 5 6 7 8 9 10 11
Data
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
Load
LDAC
Figure 1. Load controlled update (LDAC = 0)
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Wolfson Microelectronics
WM5620L, WM5620
Timing Diagrams
1 CLK 2 3 4 5 6 7 8 9 10 11
Data
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
Load
LDAC
Figure 2. LDAC controlled update
1 CLK
2
3
4
5
6
7
8
9
10
11
Data
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
Load
LDAC
Figure 3. Load controlled update (LDAC = 0) using 8-bit serial word.
1 CLK 2 3 4 5 6 7 8 9 10 11
Data
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
Load
LDAC
Figure 4. LDAC controlled update using 8-bit serial word.
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WM5620L, WM5620
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name GND RefA RefB RefC RefD Data Clk Load DACD DACC DACB DACA LDAC VDD Type Supply Analogue input Analogue input Analogue input Analogue input Digital input Digital input Digital input Analogue output Analogue output Analogue output Analogue output Digital input Supply Function Ground return and reference terminal Reference voltage input to DACA Reference voltage input to DACB Reference voltage input to DACC Reference voltage input to DACD Serial interface data Serial interface clock, negative edge sensitive Serial interface load DAC D output DAC C output DAC B output DAC A output DAC update latch control positive supply voltage
Functional Description
DAC operation Each of WM5620/L 's four digital to analogue converters (DACs) are implemented using a single resistor string with 256 taps corresponding to each of the input 8-bit codes. One end of a resistor string is connected to the GND pin and the other end is driven from the output of a reference input buffer. The use of a resistor string guarantees monotonicity of the DAC's output voltage. Linearity depends upon the matching of the resistor string's individual elements and the performance of the output buffer. The reference input buffers present a high impedance to reference sources. Each DAC has a voltage output amplifier which is programmable for gains of x1 or x 2 through the serial interface. The DAC output amplifiers feature rail to rail output stages, allowing outputs over the full supply voltage range to be achieved with a x 2 gain setting and a VDD/2 reference voltage input. Used in this way a slight degradation in linearity will occur as the output voltage approaches VDD. A power-on-reset activates at power up resetting the DACs inputs to code 0. Each output voltage is given by: Vout = Vref x CODE/256 x (1 + RNG) Where: RNG controls the output gains of x 1 and x 2 CODE is the range 0 to 255 Data Interface WM5620/L's four double buffered DAC inputs allow several ways of controlling the update of each DAC's output. Serial data is input, MSB first, into the DATA input pin using CLK, LOAD and LDAC control inputs and comprises 2 DAC address bits, an output range (RNG) bit and 8 DAC input bits. With the LOAD pin high data is clocked into the DATA pin on each falling edge of CLK. Any number of data bits may be clocked in, only the last 11 bits are used. When all data bits have been clocked in, a falling edge at the LOAD pin latches the data and RNG bits into the correct 9 bit input latch using the 2 bit DAC address. If the LDAC input pin is low, the second latch at the DAC input is transparent, and the DAC input and RNG bit will be updated on the falling edge of LOAD simultaneously with the input latch, as shown in figure 1. If the LDAC input is high during serial data input, as shown in figure 2, the falling edge of the LOAD input stores the data in the addressed input latch. The falling edge of LDAC updates the second latches from the input latches and hence the DAC outputs.
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WM5620L, WM5620
Functional Description (Continued)
Using these inputs individual DACs can be updated using one 11 bit serial input word and the LOAD pin. Using both LOAD and LDAC, all or selected DACs can be updated after an appropriate number of data words have been inputted. Figures 3 & 4 illustrate operation with the 8 clock pulses available from some microprocessors. If the data input is interrupted in this way the clock input must be held low during the break in clock pulses. The RNG bit controls the DAC output range. When RNG = 0 the output is between Vref(A,B,C,D) and GND and when RNG = 1 the range is between 2 x Vref (A,B,C,D) and GND.
Serial Input Decode
A1 0 0 1 1 A0 0 1 0 1 DAC DACA DACB DACC DACD
D7 0 0 * * 0 1 * * 1
D6 0 0 * * 1 0 * * 1
D5 0 0 * * 1 0 * * 1
D4 0 0 * * 1 0 * * 1
D3 0 0 * * 1 0 * * 1
D2 0 0 * * 1 0 * * 1
D1 0 0 * * 1 0 * * 1
D0 0 1 * * 1 0 * * 1
Output Voltage GND (1/256) x Ref (1 + RNG) * * (127/256) x Ref (1 + RNG) (128/256) x Ref (1 + RNG) * * (255/256) x Ref (1 + RNG)
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WM5620L, WM5620
Applications Information
Linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However, because the most negative supply rail is GND, the output cannot drive to a negative voltage. So when the output offset voltage is negative, the output voltage remains at ZERO volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in the transfer function shown below. This negative offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive to a negative voltage. For a DAC, linearity is measured between ZERO input code ( all inputs 0 ) and full scale code ( all inputs 1 ) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full scale code and the lowest code which produces a positive output voltage. The code is calculated from the maximum specification for the negative offset.
Effect of negative offset (single supply)
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WM5620L, WM5620
Package Descriptions
Plastic Small-Outline Package D - 8 pins shown
4.00 3.80 8
A 5
6.20 5.80
1 1.75 1.35
4 0.50 0.25 0.19 x 45O NOM 0.25
0.51 0.25 0.10 0.33 Pin spacing 1.27 B.S.C. 0O to 8O 1.27 0.40
Dimension 'A' Variations N 8 14 16 Min 4.80 8.55 9.80 Max 5.00 8.75 10.00
Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-012. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm.
Rev. 1 November 96
Wolfson Microelectronics
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WM5620L, WM5620
Package Descriptions
Dual-In-Line Package
N or P
N
0.325 0.290 0.015 Min.
1
N/2
A 0.070 Max.
0.280 0.240
0.210 Max. 105O 90O 0.014 0.008 0.150 0.115 0.005 Min. Pin spacing 0.100 B.S.C. 0.045 0.030 0.022 0.014 Seating plane
Dimension 'A' Variations N 8 14 16 20 Min 0.355 0.735 0.735 0.940 Max 0.400 0.775 0.775 0.975
Notes: A. Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width.
Rev. 1 November 96
14
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